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| analog w devices ( features adv478/adv471 (adv@) register level compatible ibm ps/2, * vga * /xga * compatible 135 mhz pipelined operation triple 8-bit d/ a converters triple 256 x 8 (256 x 24) color palette ram three 15 x 8 overlay registers on-board voltage reference rs-343a/rs-170 compatible analog outputs ttl compatible digital inputs and outputs sync on all three channels programmable pedestal (0 or 7.5 ire) standard mpu i/o interface +5 v cmos monolithic construction 68-pin plcc package applications high resolution color graphics true-color visualization cae/cad/cam image processing desktop publishing cmos 135 mhz true-color graphics triple a-bit video ram-dac adv473 i modes 24-bit true color 8-bit pseudo color 15-bit true color 8-bit true color speed grades 135 mhz, 110 mhz 80 mhz, 66 mhz general description the adv473 is a complete analog output, video ram-dac on a single cmos monolithic chip. the part is specifically designed for true-color computer graphics systems. the adv473 integrates a number of graphic functions onto one device allowing 24-bit direct true-color operation at the maxi- mum screen update rate of 13s mhz. it can also be used in other modes, induding is-bit true color and 8-bit pseudo or indexed color. the adv473 is fully ps/2 and vga register level compatible. it is also capable of implementing ibm's xga standard. ( functional block diagram sync eii:ank so s1 olo overlays i ola ro red i r7 go green i g7 bo blue i b7 clock do-d7 rd wr rso rs1 rs2 adv is a registered trademark of analog devices inc. .personal system/2 and vga are trademarks of international business machines corp. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ---- - one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 -- (continued on page 4) vrefin vrefout =t= voltage reference generator 1--+0 opa 8 lor 8 log 8. lob cro cr1 cr2 cra i adv473 obsolete
adv473 specifications (vaal = 5 v; vref = 1.235 v; rl = 37.50, cl = 10 pf; rset = 140 o. . - all specifications t min to t max 2 unless otherwise noted.) notes 'vaa=sv:ts% 2temperature range (t min to t max); oc to +70c; tj (silicon junction temperature) 05 100c. 'pixel port is continuously clocked with data corresponding to a linear ramp. 4clock and data feed through is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse includes clock and data feed through. 'ttl input values are 0 to 3 volts, with input rise/fall times 053 ns, measured at the 10% and 90% points. timing reference points at 50% for inputs and outputs. 6dac to dac crosstalk is measured by holding one dac high while the other two are making low to high and high to low transitions. specifications subject to change without notice. -2- rev. a - - parameter ail versions units test conditions/comments static performance resolution (each dac) 8 bits accuracy (each dac) integral nonlinearity :tl lsb max differential nonlinearity :tl lsb max guaranteed monotonic gray scale error :t5 % gray scale external reference :tl0 % gray scale internal reference coding binary digital inputs input high voltage, vinh 2 vmin input low voltage, vinl 0.8 vmax input current, iin :tl fla max vin = 0.4 v or 2.4 v input capacitance, cin 7 pf max f = 1 mhz, vin = 2.4 v digital outputs output high voltage, voh 2.4 vmin isource = 400 fla output low voltage, vol 0.4 vmax isink = 3.2 ma floating-state leakage current 50 fla max floating-state leakage capacitance 7 pf max analog outputs gray scale current range 20 ma max output current white level relative to black 16.74 ma min typically 17.62 ma 18.50 ma max black level relative to blank 0.95 ma min typically 1.44 ma (pedestal = 7.5 ire) 1.90 ma max black level relative to blank 0 fla min typically 5 fla (pedestal = 0 ire) 50 fla max blank level 6.29 ma min typically 7.62 ma 8.96 ma max sync level 0 fla min typically 5 fla 50 fla max lsb size 69.1 fla typ dac-to-dac matching 2 %max typically 1 % output compliance, voc 0 vmin +1.5 vmax output capacitance, cout 30 30 pf max f = 1 mhz, lout = 0 ma output impedance, rout 10 ko typ voltage reference internal voltage reference (vrefout) 1.08/1.32 v rnin/v max typically 1.235 v external voltage reference range 1.14/1.26 v rnin/v max typically 1.235 v input current, iyref (internal reference) 100 fla typ input current (external reference) 10 fla typ power supply supply voltage, v aa 4.75/5.25 v min/v max supply current, iaa 3 400 ma max 135 mhz parts 300 ma max 110 mhz parts 250 ma max 80 mhz parts 200 ma max 66 mhz parts dynamic performance clock and data feedthrough4, 5 -30 db typ glitch impulse4, 5 75 pv secs typ dac-to-dac crosstalk6 -23 db typ obsolete ) adv473 timi g ch racteristics 1 (vaal = 5 v; vref = 1.235 v; rl = 37.50, cl = 10 pf; rset = 1400. n a all specifications tmin to tma/ unless otherwise noted.) ) notes 'ttl input values are 0 to 3 volts, with input rise/fall times :5 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load :5 10 pf, dg-d7 output load :5 50 pf. see timing notes in figure 2. 2v aa = 5 v :t 5%. 'temperature range (tmin to tmax); o'c to +70'c; tj (silicon junction temperature) :5 100'c . 4t, and t4 are measured with the load circuit of figure 3 and defined as the time required for an output to cross 0.4 v or 2.4 v. sts and t6 are derived from the measured time taken by the data outputs to change by 0.5 v when loaded with the circuit of figure 3. the measured number is then extrapolated back to remove the effects of charging the 50 pf capacitor. this means that the times, ts and t6' quoted in the timing characteristics are the true values for the device and, as such, are independent of external bus loading capacitances. 6settling time does not include clock and data feedthrough. specifications subject to change without notice. ) tlo clock ro-r7, go--g7, bg-b7, olo-ol3, sg-s1, sync,blank rd,wr t tl1 dataout adv473 pin function description blank sync ) comp v refin vrefout ) vaa gnd wr rd rso, rs1, rs2 dd-d7 crd-cr7 composite blank control input (ttl compatible). a logic zero drives the analog outputs to the blanking level. it is latched on the rising edge of clock. when blank is a logical zero, the pixel and overlay inputs are ignored. composite sync control input (ttl compatible). a logical zero on this input switches off a 40 ire current source on the analog outputs. sync does not override any other control or data input; therefore, it should be asserted only during the blanking interval. it is latched on the rising edge of clock. if sync information is not required on the analog outputs, sync should be connected to ground. clock input (ttl compatible). the rising edge of clock latches the rd-r7, go-g7, bo-b7, so, sl, old-ou, sync, and blank inputs. it is typically the pixel clock rate of the video system. it is recommended that clock be driven by a dedicated ttl buffer. red, green and blue select inputs (ttl compatible). these inputs specify, on a pixel basis, the color value to be written to the dacs. they are latched on the rising edge of clock. ro, go and bo are the lsbs. unused inputs should be connected to gnd. color mode select inputs (ttl compatible). these inputs specify the mode of operation as shown in table iii. they are latched on the rising edge of clock. overlay select inputs (ttl compatible). these inputs specify which palette is to be used to provide color information. when accessing the overlay palette, the ro-r7, go-g7, bo-b7, so and sl inputs are ignored. they are latched on the rising edge of clock. olo is the lsb. unused inputs should be connected to gnd. red, green, and blue current outputs. these high impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable. full-scale adjust resistor. a resistor (rset) connected between this pin and gnd controls the magnitude of the full-scale video signal. the relationship between rset and the full-scale output current on each output is: rset (n) = 3,195 x vref (v)/iout (ma) setup = 7.5 ire) rset (n) = 3,025 x v ref (v)/iout (ma) setup = 0 ire) compensation pin. these pins should be connected together at the chip and connected through 0.1 flf ceramic capacitor to v aa' voltage reference input. this input requires a 1.2 v reference voltage. this is achieved through the on-board voltage reference generator by connecting v refout to v refin' if an external reference is used, it must supply this input with a 1.2 v (typical) reference. voltage reference output. this output delivers a 1.2 v reference voltage from the device's on-board voltage reference generator. it is normally connected directly to the vrefin pin. if it is preferred to use an external voltage reference, this pin may be left floating. up to four adv 473s can be driven from v refout' analog power. all v aa pins must be connected. analog ground. all gnd pins must be connected. write control input (ttl compatible). do-d7 data is latched on the rising edge of wr, and rsd-rs2 are latched on the falling edge of wr during mpu write operations. rd and wr should not be asserted simultaneously. read control input (ttl compatible). to read data from the device, rd must be a logical zero. rsd-rs2 are latched on the falling edge of rd during mpu read operations. rd and wr should not be asserted simultaneously. register select inputs (ttl compatible). rso-rs2 specify the type of read or write operation being performed. data bus (ttl compatible). data is transferred into and out of the device over this eight-bit bidirectional data bus. do is the least significant bit. control outputs (ttl compatible). these outputs are used to control application specific features. the output values are determined by the contents of the command register (cr). ) rev. a ---- -5- - -- -- -- clock ro-r7 bd-b7 go-g7 so, sl ) old-ou lor, log, lob rset obsolete adv473 terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level which will shut off the pic- ture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three pri- mary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. composite sync signal (sync) the position of the composite video signal which synchronizes the scanning process. composite video signal the video signal with or without setup, plus the composite sync signal. gray scale the discrete levels of video signal between reference black and reference white levels. an 8-bit dac contains 256 different lev- els while a 6-bit dac contains 64. raster scan the most basic method of sweeping a crt one line at a time to generate and to display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. setup the difference between the reference black level and the blank- ing level. sync level the peak level of the composite sync signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion which may be visually observed. circuit description mpu interface the adv473 supports a standard mpu bus interface, allowing the mpu direct access to the color palette ram and overlay color registers. three address decode lines, rsd-rs2, specify whether the mpu is accessing the address register, the color palette ram, the overlay registers, or read mask register. these controls also determine whether this access is a read or write function. table i illustrates this decoding. the 8-bit address register is used to address the contents of the color palette ram and overlay registers. table i. control input truth table ( color palette writes the mpu writes to the address register (selecting ram write mode, rs2 = 0, rsi = 0 and rso = 0) with the address of the color palette ram location to be modified. the mpu performs three successive write cycles (8 or 6 bits each of red, green, and blue), using rso-rs2 to select the color palette ram (rs2 = 0, rsi = 0, rso = i). after the blue write cycle, the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and written to the location specified by the address register. the address register then increments to the next location which the mpu may modify by simply writing another sequence of red, green, and blue data. a complete set of colors can be loaded into the palette by initially writing the start address and then performing a sequence of red, green and blue writes. the address automatically increments to the next highest location after a blue write. color palette reads the mpu writes to the address register (selecting ram read mode, rs2 = 0, rsi = 1 and rso = 1) with the address of the color palette ram location to be read back. the contents of the palette ram are copied to the red, green and blue regis- ters and the address register increments to point to the next pal- ette ram location. the mpu then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using rsd-rs2 to select the color palette ram (rs2 = 0, rsi = 0, rso = 1). after the blue read cycle, the 24/18 bit contents of the palette ram at the location specified by the address register is loaded into the red, green and blue registers. the address register then increments to the next location which the mpu can read back by simply reading another sequence of red, green, and blue data. a complete set of colors can be read back from the palette by initially writing the start address and then performing a sequence of red, green and blue reads. the address automatically increments to the next highest location after a blue read. ( ( -6- rev. a ---- rs2 rsi rso addressed by mpu 0 0 0 address register (ram write mode) 0 1 1 address register (ram read mode) 0 0 1 color palette ram 0 1 0 pixel read mask register 1 0 0 address register (overlay write mode) 1 1 1 address register (overlay read mode) 1 0 1 overlay registers 1 1 0 command register obsolete ) adv473 ') table ii. address register (addr) operation ) overlay color writes the mpu writes to the address register (selecting overlay register write mode, rs2 = 1, rsi = 0 and rso = 0) with the address of the overlay register to be modified. the mpu performs three successive write cycles (8 or 6 bits each of red, green, and blue), using rsg-rs2 to select the overlay registers (rs2 = 1, rsi = 0, rso = 1). after the blue write cycle, the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and are written to the overlay register specified by the address register. the address register then increments to the next overlay register which the mpu may modify by simply writing another sequence of red, green, and blue data. a complete set of colors can be loaded into the over- lay registers by initially writing the start address and then per- forming a sequence of red, green and blue writes. the address automatically increments to the next highest location after a blue write. overlay color reads the mpu writes to the address register (selecting overlay register read mode, rs2 = 1, rsi = 1 and rso = 1) with the address of the overlay register to be read back. the contents of the overlay register are copied to the red, green and blue registers and the address register increments to point to the next highest overlay register. the mpu then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using rso - rs2 to select the overlay registers (rs2 = 1, rs 1 = 0, rso = 1). after the blue read cycle, the 24/18 bit con- tents of the overlay register at the specified address register loca- tion is loaded into the red, green and blue registers. the address register then increments to the next overlay register which the mpu can read back by simply reading another sequence of red, green, and blue data. a complete set of colors can be read back from the overlay registers by initially writing the start address and then performing a sequence of red, green and blue reads. the address automatically incre- ments to the next highest location after a blue read. internal address register (addr) when accessing the color palette ram, the address register resets to ooh following a blue read or write cycle to ram loca- tion ffh. when accessing the overlay color registers, the address register increments following a blue read or write cycle. ) ) rev. a ---- however, while accessing the overlay color registers, the four most significant bits (since there are only is overlay registers) of the address register (addr4-7) are ignored. to keep track of the red, green, and blue read/write cycles, the address register has two additional bits (addra, addrb) that count modulo three, as shown in table ii. they are reset to zero when the mpu writes to the address register, and are not reset to zero when the mpu reads the address register. the mpu does not have access to these bits. the other eight bits of the address register, incremented following a blue read or write cycle, (addrg-7) are accessible to the mpu, and are used to address color palette ram locations and overlay registers, as shown in table ii. addro is the lsb when the mpu is accessing the ram or overlay registers. the mpu may read the address register at any time without modifying its contents or the existing read/write mode. synchronization the mpu interface operates asynchronously to the pixel port. data transfers between the color palette ram/overlay registers and the color registers (r, g, and b as shown in the block dia- gram) are synchronized by internal logic, and occur in the period between mpu accesses. the mpu can be accessed at any time, even when the pixel clock is stopped. 8-bit/6-bit color operation the command register on the adv473 specifies whether the mpu is reading/writing 8 bits or 6 bits of color information each cycle. for 8-bit operation, do is the lsb and d7 is the msb. for 6-bit operation, color data is contained on the lower six bits of the data bus, with do being the lsb and d5 the msb of color data. when writing color data, d6 and d7 are ignored. during color read cycles, d6 and d7 will be a logical "0." it should be noted that when the adv473 is in 6-bit mode, full- scale output current will be reduced by approximately 1.5% rel- ative to the 8-bit mode: this is the case since the 2 lsbs of each of the. three dacs are always set to zero in 6-bit mode. -7- value rs2 rsi rso addressed by mpu addra,b (counts modulo 3) 00 x 0 i red value 01 x 0 i green value 10 x 0 i blue value addrg-7 (counts binary) ooh-ffh 0 0 i color palette ram xxxx 0000 i 0 i reserved xxxx 0001 i 0 1 overlay color 1 xxxx 0010 i 0 1 overlay color 2 . xxxx 1111 1 0 1 overlay color 15 obsolete adv473 command register (cr) the adv473 has an internal command register (cr). this reg- ister is 8 bits wide, crd-cr7 and is directly mapped to the mpu data bus on the part, do-d7. the command register can be written to or read from. it is not initialized, therefore it must be set. figure 4 shows what each bit of the cr register controls and shows the values it must be programmed to for various modes of operation. color modes the adv473 supports four color modes, 24-bit true-color, is-bit true-color, 8-bit true-color and 8-bit pseudo-color. the mode of operation is determined by the so and 51 inputs, in conjunction with cr7 and cr6 of the command register. so and si are pipelined to maintain synchronization with the video data. table iii illustrates the modes of operation. table iii. color operation modes ( ( x = don't care ( figure 4. command register (cr) -8- rev. a ol3-olo 81,80 cr7, cr6 mode r7-ro g7-go b7-bo 1111 xx xx overlay color 15 xxh xxh xxh 0001 xx xx overlay color 1 xxh xxh xxh 0000 00 00 24-bit true-color r7-ro g7-go b7-bo 0000 00 01 24-bit true-color r7-ro g7-go b7-bo 0000 00 10 24-bit true-color r7-ro g7-go b7-bo 0000 00 11 reserved reserved reserved reserved 0000 01 00 24-bit true-color bypass r7-ro g7-go b7-bo 0000 01 01 24-bit true-color bypass r7-ro g7-go b7-bo 0000 01 10 24-bit true-color bypass r7-ro g7-g0 b7-bo 0000 01 11 reserved reserved reserved reserved 0000 10 00 8-bit pseudo-color (red) p7-po ignored ignored 0000 10 01 8-bit pseudo-color (green) ignored p7-po ignored 0000 10 10 8-bit pseudo-color (blue) ignored ignored p7-po 0000 10 11 is-bit true-color orrrrrgg gggbbbbb ignored 0000 11 00 8-bit true-color bypass (red) rrrgggbb ignored ignored 0000 11 01 8-bit true-color bypass (green) ignored rrrgggbb ignored 0000 11 10 8-bit true-color bypass (blue) ignored ignored rrrgggbb 0000 11 11 is-bit true-color bypass orrrrrgg gggbbbbb ignored i ( cr7 1 cr6 ) i ( cr5) (cr4) i ( cr3 i cr2 i cr1 t cro 1 i color mode select (see table iii) control outputs pedestal enable these bits are output control (setup) onto the cr3-cro pins crs 0 0 ire 1 7.sire 8-bit/6-bft color select cr4 0 6-bit 1 a-bit obsolete adv473 ) video modes 24-bit true-color mode twenty-four bits of rgb color information may be input into the adv473 every clock cycle. the 24 bits of pixel information are input via the rd-r7, go-g7, and bo-b7 inputs. ro-r7 address the red color palette ram, go-g7 address the green color palette ram, and bo-b7 address the blue color palette ram. each ram provides 8 bits of color information to the corresponding d/a converter. the pixel read mask register is used in this mode. 24.bit true-color bypass mode twenty-four bits of pixel information may be input into the adv473 every clock cycle. the 24 bits of pixel information are input via the rd-r7, go-g7, and bo-b7 inputs. ro-r7 drive the red dac directly, go-g7 drive the green dac directly, and bo-b7 drive the blue dac directly. the color palette rams and pixel read mask register are bypassed. 8-bit pseudo-color mode eight bits of pixel information may be input into the adv473 every clock cycle. the 8 bits of pixel information (po-p7) are input via the ro-r7, go-g7 or bo-b7 inputs, as specified by cr7 and cr6. all three color palette rams are addressed by the same 8 bits of pixel data (pd-p7). each ram provides 8 bits of color information to the corresponding d/a converter. the pixel read mask register is used in this mode. 8-bit true-color bypass mode eight bits of pixel information may be input into the adv473 every clock cycle. the 8 bits of pixel information are input via the ro-r7, go-g7 or bo-b7 inputs, as specified by cr7 and cr6. ) table iv. 8-bit true-color bypass video input format ) as seen in the table, 3 bits of red, 3 bits of green, and 2 bits of blue data are input. the 3 msbs of the red and green dacs are driven directly by the inputs, while the 2 msbs of the blue dac are driven directly. the 5 lsbs for the red and green dacs, and the 6 lsbs for the blue dac, are a logical zero. the color palette rams and pixel read mask register are bypassed. ) rev. a is-bit true-color bypass mode fifteen bits of pixel information may be input into the adv473 every clock cycle. the 15 bits of pixel information (5 bits of red,s bits of green, and 5 bits of blue) are input via the ro-r7 and go-g7 inputs. table v. is-bit true-color video input format pixel inputs r7 r6 r5 r4 r3 r2 rl ro g7 g6 g5 g4 g3 g2 gl go input format 0 r7 r6 r5 r4 r3 g7 g6 g5 g4 g3 b7 b6 b5 b4 b3 the 5 msbs of the red, green, and blue dacs are driven directly by the inputs. the 3 lsbs are a logical zero. the color palette rams and pixel read mask register are bypassed. is-bit true-color mode fifteen bits of pixel information may be input into the adv473 every clock cycle. the 15 bits of pixel information are input to the device via ro-r7 and go-g7 according to table v. this input data points to the top 32 locations of the color palette ram, i.e., locations 223 to 255. the is-bit pixel input data indexes a 24-bit red, green and blue value which is clocked to the three dacs. overlays the overlay inputs, olo-ol3, have priority regardless of the color mode as shown in table iii. pixel read mask register the 8-bit pixel read mask register is implemented as three 8-bit pixel read mask registers, one each for the ro-r7, go-g7, and bo-b7 inputs. when writing to the pixel read mask register, the same data is written to all three registers. the read mask regis- ters are located just before the color palette rams. thus, they are used only in the 24-bit true-color and 8-bit pseudo-color modes since these are the only modes that use the color palette rams. the contents of the pixel read mask register, which may be accessed by the mpu at any time, are bit-wise logically anded with the 8-bit inputs prior to addressing the color palette rams. bit do of the pixel read mask register corresponds to pixel input po (ro, go, or bo depending on the mode). bit do also corresponds to data bus bit do. -9- ro-r7 go-g 7 bo-b7 inputs inputs input inputs selected selected selected format r7 g7 b7 r7 r6 g6 b6 r6 r5 g5 b5 r5 r4 g4 b4 g7 r3 g3 b3 g6 r2 g2 b2 g5 ri gl bl b7 ro go bo b6 obsolete adv473 ma 26.67 9.05 7.62 0.00 v 1.000 92.5 ire 0.340 0.286 7.5 ire 40 ire 0.000 note: 750 doubly terminated load, setup = 7.5 ire, vref = 1.235 v, rset = 1400 rs-343a levels and tolerances assumed on all levels. ma 25.24 v 0.950 7.62 i 0.286 figure 5. composite video output waveform (setup = 7.5 ire) table vi. video output truth table (setup = 7.5 ire) note typical with full-scale lor, log, lob = 26.67 ma, setup = 7.5 ire, vref = 1.235 v, rset = 140 d. external voltage reference adjusted for 26.67 ma full-scale output. 100 ire 43 ire 0.00 i 0.000 note: 750 doubly terminated load, setup = 0 ire, vref = 1.235 v, rset = 1400 rs-343a levels and tolerances assumed on all levels. figure 6. composite video output waveform (setup = 0 ire) table vii. video output truth table (setup = 0 ire) note typical with full-scale lor, log, lob = 25.24 ma, setup = 0 ire, vref = 1.235 v, rset = 140 d. external voltage reference adjusted for 26.67 ma full-scale output. -10- ~- white level black level blank level sync level white level black/blank level sync level --- ( ( ~ ( rev. a lout dac description (ma) sync blank input data white 26.67 i i ffh data data+9.05 1 1 data data-sync data+ 1.44 0 1 data black 9.05 1 1 doh black-sync 1.44 0 1 doh blank 7.62 1 0 xxh sync 0 0 0 xxh lout dac description (ma) sync blank input data white 25.24 1 1 ffh data data+7.62 1 1 data data-sync data 0 1 data black 7.62 1 1 ooh black-sync 0 0 1 doh blank 7.62 1 0 xxh sync 0 0 0 xxh obsolete adv473 pc board layout considerations the layout should be optimized for lowest noise on the adv473 power and ground lines by shielding the digital inputs and pro- viding good decoupling. the lead length between groups of v aa and gnd pins should be minimized so as to minimize inductive ringing. ground planes the ground plane should encompass all adv473 ground pins, current/voltage reference circuitry, power supply bypass cir- cuitry for the adv473, the analog output traces, and all the digital signal traces leading up to the adv473. power planes the adv473 and any associated analog circuitry should have its own power plane, referred to as the analog power pl!lne. this power plane should be connected to the regular pcb power plane (v cd at a single point through a ferrite bead, as illus- trated in figures 7 and 8. this bead should be located within three inches of the adv473. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv473 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. supply decoupling for optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera- tion, to reduc.e the lead inductance. best performance is obtained with a 0.1 f.lf ceramic capacitor decoupling each of the two groups of v aa pins to gnd. these capacitors should be placed as close as possible to the device. it is important to note that while the adv473 contains circuitry to reject power supply noise, this rejection decreases with fre- quency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and should consider using a three-terminal voltage regula- tor for supplying power to the analog power plane. rev. a digital signal interconnect the digital inputs to the adv473 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv473 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cd, and not to the analog power plane. power supply decoupling (o.1~f capacitor for each vaef group) +5v iv aa) 0.1~~ 7 9 analog power plane +5v <':' aa) 1kq (1% metal) l1 (ferrite bead) ~0.1~f ad5897s - 0.1~f {1.2vaef).i. 7 co-axial cable (75q) monitor (crt) d 75q bnc connectors component c1-c5 c6 l1 r1, r2, r3 r4 rset z1 description 0.1~f ceramic capacitor 10~f tantalum capacitor ferrite bead 75q 1% metal film resistor 1kq 5% resistor 1% metal film resistor 1.23v voltage reference vendor part number erie rpe112z5u104m50v mallory csr13g106km fair-rite 2743001111 ad589jn figure 7. typical connection diagram (external voltage reference) -11- -~ vaa comp comp vaefout' vaefin ' adv473 rset rset i lor i 140q log i lobi gnd obsolete adv473 analog signal interconnect the adv473 should be located as close as possible to the out- put connectors to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. for maximum performance, the analog outputs should each have a 75 11 load resistor connected to gnd. the connection between the current output and gnd should be as close as pos- sible to the adv473 to minimize reflections. for more information on circuit board design and layout, see application note entitled "design and layout of a video graph- ics system for reduced emi" available from analog devices, publication no. e1309-15-1o/89. power supply decoupling (o.1~f capacitor for each vref group) +sv iy aa) o.1~~ v 7 analog power plane vaa comp comp l1 (ferrite bead) ~o.1~f vrefout vrefin 7 co-axial cable (7sq) i 7sq d adv473 monitor (crt) rset 140q rset lor log lob gnd bnc connectors component c1 - c5 c6 l1 r1, r2, r3 rset description o.1~f ceramic capacitor 10~f tantalum capacitor ferrite bead 7sq 1% metal film resistor 1% metal film resistor vendor part number erie rpe112z5u104msov mallory csr13g106km fair-rite 2743001111 figure 8. typical connection diagram (internal voltage reference) package thermal considerations in certain circumstances, the 135 mhz version of the adv473 may require forced air cooling or the addition of a heatsink. the 68-pin plcc has a heat resistance characteristic as shown in table viii. it should be noted that infonnation on package thennal character- istics published herein may not be the most up to date at the time of reading this. advances in packaging technology will inevitably lead to improvements in thennal data. please contact your local sales office for the most up-to-date infonnation. table viii. thermal resistance vs. airflow outline dimensions dimensions shown in inches and (mm). plastic leaded chip carrier (p-68a) i 0.995 (25.27) 0.175 (4.45) . 0.885(22.48)50 . 0.189(4.29) 9nnnnnnnnnnnnnnnnn6111 _r- 10 / 0 ~o i ide~~i~ier i 1f=i:.1 0.050 (1.27) .tvp top view 0.925 (23.50) ~ .1 0.019 (g.48) . 0.017 (0.43) .10.~9(0.74) .0.027 (0.89) 26 ..j44 43 .j 27 f. -i-i- 0.104 (2.64) tvp 0.954 (24.23) 0.950 (24.13) so -12- rev. a m ~ j 'i' <0 ,.... u ") ) ) |
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